1. Field of the Invention
The present invention relates to data transfer through a communication system channel, and, more particularly, to detection of data information from a recording medium.
2. Description of the Related Art
A read channel component is an integrated circuit (IC) of a computer hard disk (HD) drive that encodes, detects, and decodes data, enabling a read/write head to correctly i) write data to the disk drive and ii) read back the data. The disks in an HD drive have a number of tracks, each track consisting of i) user (or “read”) data sectors and ii) control (or “servo”) data sectors embedded between the read sectors. Information of the servo sectors is employed to position the head (e.g., a magnetic recording/playback head) over a track so that the information stored in the read sector can be retrieved properly.
A servo sector typically comprises a servo preamble, an encoded servo address mark (SAM), encoded Gray data, a burst demodulation (demod) field, and a repeatable run-out (RRO) field. The servo preamble allows for timing recovery and gain adjustment of the written servo data. The SAM is an identifier of fixed bit-length that identifies the beginning of the servo data, with the value for this identifier being the same for all servo sectors. For some prior art systems, a 9-bit SAM is written (after encoding) between the servo preamble field and the servo Gray data.
Gray data represents the track number/cylinder information and provides coarse positioning information for the head. The burst demod field provides fine positioning information for the head. RRO field data provides head positioning information that is i) finer than that provided by Gray data and ii) coarser than that provided by the burst demodulation fields. Specifically, RRO field data is typically employed for compensation when the head does not follow a circular track around the disk. The read sector comprises a read preamble, a read address mark (RAM), and encoded user data. The read preamble also provides for timing recovery and gain adjustment, and the RAM identifies the read sector user data.
Servo information is encoded by one or more encoders, each encoder converting M input bits (an input data block) into N output symbols (an output codeword). The encoded servo information is written to the disk and read back by a magnetic recording head. When the head of a recording system reads data from a sector of an HD, the data is provided as an analog signal (readback signal) that is subsequently level-adjusted, equalized, and sampled for further digital signal processing to detect and decode the servo information.
The readback data is equalized to a desired target partial response by an equalizer configured as a continuous time filter (CTF) followed by a discrete-time finite impulse response (FIR) filter. The sampling of the CTF output signal uses timing information generated by a digital phase-locked loop (DPLL) locked to the symbol rate (T). The output samples of the equalizer are quantized to digital sample values (‘Y’ values) using an A/D converter (ADC). The ‘Y’ values are applied to a data detector (e.g., threshold detector or Viterbi detector). A SAM detector then searches for the SAM bit pattern in the detected data. Once SAM is detected, the Gray code decoder decodes the data following the SAM data as Gray data. The RRO data detector and burst demodulator also employ these ‘Y’ values.
Since servo Gray data can be successfully recovered only after the SAM is detected, accurate detection of the SAM is relatively important. Consequently, reducing the SAM miss rate (rate of failed SAM detection) and the false SAM rate (rate of incorrect SAM detection) is desirable. Although low SAM miss rate and false SAM rate are important, better performance results for higher SAM miss rate than for higher false SAM rate.
As a higher number of bits are examined for SAM detection, the false SAM rate decreases, but the SAM miss rate increases. Similarly, as a lower number of bits are examined, the false rate increases, but the SAM miss rate decreases. Consequently, for a certain number of bits (L) for SAM detection, a given design attempts to improve the false SAM rate without an increase in format overhead (i.e., without increasing L).
For an L-bit wide SAM encoded with a wide biphase code, [s(1) s(2) s(3) . . . s(L)] denotes the L-bit pattern used for the SAM, where s(.) is either a “0” or a “1”. A wide biphase code encodes, for example, a “0” to “1100” and a “1” to “0011”. Typically, a threshold detector is employed to detect wide biphase-encoded information. The readback signal exhibits either a positive peak or a negative peak at the codeword boundary (every 4T, for the above example encoding) after equalization to a target partial response. Thus, by having a threshold of zero at the codeword boundary, if the received sample is greater than the threshold, then the data bit is detected and decoded as a “1”; otherwise, the data bit is detected and decoded as a “0”.
A prior art SAM detector for detecting an L-bit SAM operates as illustrated in FIG. 1. Every 4T (at the codeword boundary), the detected bit (1 or 0) is shifted into L-bit shift register 101 (which is initialized to L 1's before detection begins). Detected bits are denoted by d(.) in FIG. 1. The L bits in shift register 101 are then compared by L-bit comparator 103 with a copy of the L-bit pattern used for the SAM [s(1) s(2) . . . s(L)] that is stored in register 102. If the bit patterns of shift register 101 and register 102 match, then SAM detection is declared. Otherwise, the detection and shifting process continues until the SAM is found.